This section is intended to provide a background or context to the invention that is recited in the claims. The description herein may include concepts that could be pursued, but are not necessarily ones that have been previously conceived, implemented or described. Therefore, unless otherwise indicated herein, what is described in this section is not prior art to the description and claims in this application and is not admitted to be prior art by inclusion in this section.
The following abbreviations that may be found in the specification and/or the drawing figures are defined as follows:
CPU central processing unit
eMMC embedded multimedia card
exFAT extended file allocation table
LBA logical block address
MMC multimedia card
RAM random access memory
SCSI small computer system interface
SD secure digital
SW software
UFS universal flash storage
Various types of flash-based mass storage memories currently exist. A basic premise of mass storage memory is to hide the flash technology complexity from the host system. A technology such as eMMC is one example.
FIG. 1A reproduces FIG. 2 from JEDEC Standard, Embedded MultiMediaCard (eMMC) Product Standard, High Capacity, JESD84-A42, June 2007, JEDEC Solid State Technology Association, and shows a functional block diagram of an eMMC. The JEDEC eMMC includes, in addition to the flash memory itself, an intelligent on-board controller that manages the MMC communication protocol. The controller also handles block-management functions such as logical block allocation and wear leveling. The interface includes a clock (CLK) input. Also included is a command (CMD), which is a bidirectional command channel used for device initialization and command transfers. Commands are sent from a bus master to the device, and responses are sent from the device to the host. Also included is a bidirectional data bus (DAT[7:0]). The DAT signals operate in push-pull mode. By default, after power-up or RESET, only DAT0 is used for data transfer. The memory controller can configure a wider data bus for data transfer using either DAT[3:0] (4-bit mode) or DAT[7:0] (8-bit mode).
One non-limiting example of a flash memory controller construction is described in “A NAND Flash Memory Controller for SD/MMC Flash Memory Card”, Chuan-Sheng Lin and Lan-Rong Dung, IEEE Transactions of Magnetics, Vol. 43, No. 2, February 2007, pp. 933-935 (hereafter referred to as Lin et al.) FIG. 1B reproduces FIG. 1 of Lin et al., and shows an overall block diagram of the NAND flash controller architecture for a SD/MMC card. The particular controller illustrated happens to use a w-bit parallel Bose-Chaudhuri-Hocquengham (BCH) error-correction code (ECC) designed to correct random bit errors of the flash memory, in conjunction with a code-banking mechanism. Of particular interest herein are the various RAM memories (e.g., buffer RAM, bank RAM, common RAM) that form part of the controller architecture.
Reference may also be made to US Patent Application Publication 2008/0228984, Sep. 18, 2008, “Single-Chip Multi-Media Card/Secure Digital (MCC/SD) Controller Reading Power-On Boot Code from Integrated Flash Memory for User Storage”, I-Kang Yu et al. This publication describes another example of a flash controller where a Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than booting from an internal ROM coupled to the CPU, a boot loader is transferred by direct memory access (DMA) from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program. This approach is said to enable the microcontroller ROM to be eliminated or minimized.
Also of potential interest is an application note AN2539 “How to boot an embedded system from an eMMC™ equipped with a Microsoft FAT file system”, Numonyx B. V., November 2008. This application note in Appendix A provides an overview of eMMC, and in Appendix B provides an overview of FAT.